FIG. 1 shows a flash memory device 100 that typically includes one or more memory arrays or sub-arrays, shown as 102, that is organized into n rows and m columns of flash memory cells. For example, an exemplary 8 Mbit memory array has n=4096 rows and m=2048 columns. A 23-bit address for a particular one of the memory cells in the array 102 is applied to a predecoder 104. The predecoder 104 provides 12 row address bits on a row-address bus 106 to a row decoder 108. The predecoder 104 also provides 11 address bits on a column-address bus 110 to a column decoder 112.
For accessing a particular row, the row decoder 108 provides a row select signal to one of 4096 row decoder output lines in a bus 114, where each one of the 4096 row decoder output lines is coupled to a respective one of 4096 row select terminals of the memory array 102.
The 2048 columns are arranged in 16 groups of 128 columns. The columns are coupled on a 2048-line bus 116 between the 2048 columns of the memory array 102 and 2048 respective decoders in the column decoder 112. The 2048 decoders are coupled to sense and senses circuitry 120 through a 2048-line bus 119. The sense and sense circuitry 120 is coupled to sixteen input/output (I/O) lines on a data bus 122. The sense amplifier circuits 120 are used to read the contents of the selected memory cells. During a write or modify operation, the sense amplifier circuits 120 are used to verify the correctness of the contents of modified cells.
In general, the number of data I/O lines of a memory device can be 1 bit, a byte (8 bits), a word (16 bits) or a double word (32 bits). As mentioned previously, the memory columns are arranged in groups, where each group corresponds to one particular output bit. For example, if the data output of a memory device is a 16-bit word then the columns internally are arranged in 16 groups, where each group has a number of columns assigned to it. During a read operation or a verify operation, 16 columns are selected, one from each group of columns, along with a row selection, so that 16 memory cells will be read or verified. Each of the 16 cells provides one of the 16 bits of the data output. This means that for each address applied to the memory device at lease 16 flash memory cells are selected in parallel.
FIG. 2 is a diagram that illustrates how columns are arranged in groups corresponding to one bit of a 16-bit output word. For example, a memory array with 2048 columns is arranged in 16 column groups with 128 columns related to one of the sixteen I/O outputs for each group. A typical column group 130 for the <0> bit of a 16 bit word having bit<0> to bit<15> is illustrated in FIG. 2. The 128 columns lines from the typical column group 130 are coupled through a bus 132 having 128 column lines to corresponding typical column decoder/sense amplifier circuits 134, which have a DATA<0> I/O bit provided on a signal line 136. Fifteen other similar column groups and corresponding column decoder/sense amplifier circuits provide respective DATA<1> to DATA <15> I/O bits.
During the manufacture of flash memory devices, some flash memory cells in the memory array 102 can be defective and operate improperly. A defective memory cell can prevent memory data designated for storage in that defective memory cell from being correctly read or modified. To reduce the effect of defective flash memory cells on product yield, redundant flash memory cells are often employed to selectively replace normal flash memory cells that exhibit incorrect behavior during a device testing phase. To store addresses of defective flash memory cells, one or more non-volatile redundant address registers are provided.
FIG. 3 illustrates a conventional flash memory redundant column system 150 for a memory array. The memory array includes a regular flash memory array 152 that is coupled to a regular column decoder circuit 154. A redundant memory array 156 is coupled to a redundant column decoder 158. The regular column decoder 154 is coupled to regular senses 160, and the redundant column decoder 158 is coupled to redundant senses 162. The regular senses 160 have, for example, sixteen I/O lines 164 that are used for transferring data into and out of the memory array system.
A command user interface (CUI) circuit 170 receives a write enable (WE) signal at a terminal 172 and provides to the senses 160 on signal line 174 an output signal LOAD_PL. The LOAD_PL signal is a signal pulse that is generated by the rising edge of the WE signal. The LOAD_PL pulse triggers the latching of data and addresses in the regular senses 160.
Redundant address registers 180 store the addresses of defective memory cells, which are provided to a redundant logic circuit 182. Input memory addresses are also provided to the redundant logic circuit 182. The redundant logic circuit 182 compares the input memory addresses to addresses of defective regular memory cells provided by the redundant address registers 180. For a positive comparison, or match, the redundant logic circuit 182 also activates a particular one of 2048 SENSE_DISAB signals on a 2048-bit bus 184 to disable a sense for a defective memory cell and also to activate one of 4 (in this example) redundant senses 162 with one of four REDUNDANT_ON signals provided on a bus 166.
In summary, the input addresses associated with a given read or write memory operation are compared to all the addresses stored in the redundant address registers 180. If an input address matches one of the addresses of a defective memory cell that is stored in the redundant address registers 180, the redundant logic circuit 182 switches off a normal address decoding path with one of the 2048 SENSE_DISAB signals on the 2048-bit bus 184 and an associated sense circuit and alternatively enables the redundant senses 162.
Conventionally, during a write, or programming, operation, data to be written into flash memory locations are stored locally in each sense circuit for a verify operation. The sense circuit compares the sense output, after the verify operation, with the data to be written and, according to the comparison result, controls the associated bit line voltage to either enable or to disable the write operation. Each of the redundant memory cells has its own sense and sense circuit. An external input address applied to the memory is compared with the contents of the redundant address registers 180. If a match occurs with a column address of a defective memory cell stored in the redundant address registers, redundant circuits are activated. The redundant circuits disable the sense and the sense circuits associated with the defective cell and activate the sense and sense circuits for the redundant cell.
During a write, or programming, operation, the number of senses activated corresponds to the number of cells to be programmed in parallel. This number can be very high in some flash memory devices to allow a high program throughput. In order to minimize the number of redundant cells required to be added to the memory array, it is more efficient to allow for replacement of one single sense circuit with a redundant sense circuit. In this way, only a defective memory cell is replaced with a redundant cell, while all the other working cells that share the same address of the defective memory cell, are not replaced. For example, for a 2048 bit program buffer for 2048 cells written in parallel, the memory device has 2048 senses and sense circuits that perform the verify operation and that control the bit line voltage. This requires a 2048-bit bus to be able to switch off any one of the 2048 senses. If there are sixteen I/O bits for the memory device, there will be 128 control wires for each one of the sixteen I/O bits. As a result, a large amount of circuits are needed to be able to load and activate every one of the redundant senses.
In prior art redundant column systems, an address comparison is not performed during the command cycle. In fact, in prior art devices, data provided by a user are loaded in the senses of a program buffer and address comparisons are performed at a later time during the execution of an embedded program algorithm. Therefore, in prior art systems, the number of signal lines that are required to disable the senses of the program buffer is equal to the number of senses. In flash memory devices the program command is clocked by an external signal provided by the user, commonly called “write enable” (WE). The user, in the case of a 2048 bits program buffer, applies 128 words (data to be programmed) along with 128 addresses (location of the memory where the data have to be written). The rising edge of “write enable” signal latches the address and the data given to the memory. Thus, at each cycle of WE signal, a single 16 bit word to be programmed along with its address is applied to the memory. In this example, to fill completely the program buffer, 128 WE cycles are needed.